1. Field of the Invention
The present invention relates to a printed circuit board and an electric device suitable for mounting on a printed circuit board. More particularly, the present invention relates to improvements in the configuration of pad electrodes on a printed circuit board and the shape of leads found in IC (integrated circuit) packages such as LSI (large scale integration) packages.
2. Description of the Related Art
Recently, industrial machines and tools, computers, and the like have been required to be smaller and perform more advanced or complicated functions. Accompanied with this situation, current electric devices (such as semiconductor devices) are manufactured to be small and integrated. The printed circuit boards on which such electric devices are to be mounted are often required to be correspondingly small in size.
FIG. 1 shows a partial sectional view of a conventional printed circuit board 300. Printed circuit board 300 comprises an insulating board 302 and circuit patterns 304 composed of conductive (e.g., copper) films formed on the insulating board. Circuit patterns 304 include a plurality of land portions, i.e., pad electrodes. An electric device 306, such as a semiconductor device, is mounted on printed circuit board 300. Electric device 306 has a plurality of leads which are soldered to corresponding pad electrodes of circuit patterns 304, respectively. One of the leads, designated by the reference numeral 308, and its respective pad electrode 310, are shown in FIG. 1.
As shown in FIG. 1, a surface 312 of pad electrode 310 is soldered together with one end portion 314 of lead 308. Surface 312 is parallel to the upper surface of insulating board 302, such that pad electrode 310 has a uniform thickness. Soldered surface 312 is in contact with end portion 314 and bonded to lead 308 by solder material 316.
According to the conventional technology described above, the amount of solder material disposed between soldered surface 312 of pad electrode 310 and end portion 314 of lead 308 is very small. This is because semiconductor devices are currently manufactured to be integrated and minute with narrow lead widths, and the end portion 314 of leads in such devices is parallel to the surface of insulating board 302. Due to the small amount of solder material present between surface 312 and end portion 314, a sufficient lead pull strength between lead 308 and pad electrode 310 cannot be fully attained.
The foregoing problem seriously affects the performance and manufacturing of devices such as the Quad Flat Package (QFP) type semiconductor device 400 illustrated in FIGS. 2(a) and 2(b). These figures show a plan view and a partial side view of QFP type semiconductor device 400, respectively. As is apparent from FIGS. 2(a) and 2(b), the sectional size of each lead 402 of QFP semiconductor device 400 is small, such as 0.2 mm.times.0.2 mm or 0.1 mm.times.0.2 mm, and the spacings between such leads are narrow in dimension (e.g., 0.4 mm to 0.5 mm).
FIG. 2(b) illustrates that QFP type semiconductor device 400 is mounted on a printed circuit board 408. With reference to FIG. 2(b), it is difficult to ensure that a fillet portion of solder material 404 will be formed at an edge portion of lead 402 such that the lead will be securely bonded to pad electrode 406.
As is apparent from FIG. 2(a), the leads 402 of QFP type semiconductor device 400 are not always properly bonded to their respective pad electrodes 406 due to, for example, various errors in the manufacturing process and the like. As a result, a relative alignment error between each lead 402 and its respective pad electrode 406 occurs, and a lead pull strength between each lead 402 of QFP type semiconductor device 400 and printed circuit board 408 is largely decreased. Reference numeral 402a of FIG. 2(b) is representative of a lead that is not securely bonded to its respective pad electrode.
Japanese Patent Disclosure (Kokai) No. 3-104148 describes a method to improve a lead pull strength by forming a step portion in one end portion of a lead. This document contends that by forming a step portion in one end portion of a lead, a soldered portion having a greater thickness can be formed and the lead pull strength between a lead and a land portion of a printed circuit board can be improved.
The method of this document is deficient, however, in that it requires the formation of a step portion in each lead, thereby complicating the manufacturing process. The manufacturing process becomes even more difficult when the number of leads being fabricated is increased or when leads having minimized dimensions are being fabricated. A further deficiency associated with this method is that it cannot sufficiently resolve the above-described problem resulting from relative alignment error.
The above-described problem resulting from relative alignment error is also observed in a Pin Grid Array (PGA) type semiconductor device 500, as illustrated in FIGS. 3(a), 3(b), and 3(c). These figures show, respectively, a side view and a plan view of PGA type semiconductor device 500, and a partial magnified side view of soldered portions of leads extending out from the device.
PGA type semiconductor device 500 has a plurality of lead pins 502, which are regularly arrayed in a lattice located at the bottom surface of its body. The configuration of each lead pin 502, and the length of such lead pins, are the same. Each lead pin 502 is mounted so as to contact with a respective pad electrode 504 formed on a printed circuit board 506.
According to the structure shown in FIG. 3(c), a relative alignment error between each lead pin 502 and its respective pad electrode 504 occurs because the accuracy of forming lead pins 502 or pad electrodes 504 at pre-designed sizes, and the alignment of each lead pin 502 and its respective pad electrode 504, are subject to deterioration an accompanied by effects resulting from the fabrication of lead pins which are small or minute. Due to the foregoing factors, it is difficult to properly carry out the soldering of each lead pin 502 to its respective pad electrode 504. Accordingly, the lead pull strength between such lead pins and their corresponding pad electrodes is largely decreased.
In light of the foregoing problems, a new method which minimizes or eliminates deterioration of the lead pull strength, without requiring complex manufacturing techniques, is desired.